1. Field of the Invention
The present application relates to integrated circuit design and more specifically to power consumption analysis in the integrated circuit designs.
2. Description of the Related Art
Generally, in an integrated circuit, signals are routed through various nets for large distances within the integrated circuit. These nets propagate signals between various functional blocks (e.g., arithmetic and logic unit, floating point unit and the like) within the integrated circuit and/or between peripherals and the functional blocks within the integrated circuit. In a typical synchronous design, logic operations (e.g., switching or the like) are performed following a common event (e.g., rising or falling of the clock signal or the like). If the design requires these functions to be completed within one clock period then these operations must complete before the next common event (e.g., rising or falling of the next clock signal or the like). Thus, if a signal has to propagate from one functional block to another in one cycle time then the signal must start at the rising (or falling) edge of a clock cycle and reach its destination before the rising (or falling) edge of the next clock cycle.
The integrity of the signal (e.g., timings, signal slew requirement or the like) can be affected when the signal is routed through large distances within the integrated circuit. Typically, repeaters are inserted in the signal nets to ensure and maintain signal integrity. Sometimes, the delay in a signal net may become larger than the specified cycle time. Typically, in such cases, devices (e.g., flops, repeaters or the like) are inserted in the signal net to break the signal net into two separate paths, each one of which meets the cycle time requirement. Repeaters and flops are large devices that can draw significant switching current and hence consume large amount of switching power.
An accurate determination of the power consumption of repeaters and flops is required to design a robust power distribution for the integrated circuit. The accurate measures of power consumptions can be used to provide specifications for the design of a cooling system for the integrated circuit and to determine the overall power requirement of the system. Typically, the power consumption is determined after the integrated circuit design layout is completed and verified by circuit designers. If power consumption discrepancy is discovered after the layout is verified then the redesign effort to ameliorate the situation can be detrimental to design schedule because it adds significant delay (in some cases, months) into the design cycle. It is important to know the power consumption levels of each device (e.g., repeater, flop or the like) during the top level signal routing phase of the integrated circuit design cycle so that the designers can select repeaters and flops accordingly to maintain the design target for total power consumption of the integrated circuit.
Current power analysis tools provide conservative estimates of power consumption. Some tools require the availability of a complete and final design layout and that the layout must be free of all inaccuracies (e.g., power to ground shorts, power to signal shorts and the like). Further, these tools require information about the activity level for each block within the circuit design. The problem with these tools is that, they can only be used at the very end of the design cycle when the scope for making changes to the existing design generally do not exist and further, it takes a long time to generate the data for power consumption analysis by these tools.
Some other tools provide an estimate of the power consumption for the circuit design. The power consumed in the repeaters and flops is estimated by counting the number of repeaters and flops and the total power that can be consumed by each device is summed to estimate the total power that may be consumed by the design. The sum of total power consumed by each device is heuristically scaled by a factor that can be based on an estimation of the number of repeaters or flops that can switch in one clock period. The problem with these tools is that the analysis assumes that all the repeaters and flops switch at the same time. Thus, the estimates can be inaccurate and pessimistic. Therefore, an apparatus and a method are needed to accurately determine the power consumption of the integrated circuit design during high level design cycle.